1. Field of the Invention
The invention relates to a dynamic random access memory (DRAM), and more particularly to a method of manufacturing an electrostatic discharge (ESD) protective circuit for DRAM for preventing current leakage and an operational error.
2. Description of the Related Art
In IC processing, electrostatic discharge has been a main factor causing damage to ICs including deep sub-micron ICs. Therefore, it is urgently desired to increase the efficacy of electrostatic discharge protective circuits in the semiconductor industry.
Generally, in a process for manufacturing a DRAM with a conventional capacitor over bit-line (COB) structure, an electrostatic discharge (ESD) protective circuit for protecting the DRAM against damage from an electrostatic discharge is formed therein. Referring to FIG. 1, an electrostatic discharge protective circuit for DRAM is shown. In FIG. 1, the gate of an MOS transistor 10 is electrically coupled to the source (or drain) thereof and then to ground Vss. The drain (or source) of the MOS transistor 10 is electrically coupled to an internal circuit 20 and in input port INP. With regard to the operation of the electrostatic discharge protective circuit, when the potential of a signal or electrostatic charges on the input port INP is located within a safe range, the signal or the electrostatic charges can be directly transmitted into the internal circuit 20. On the other hand, if the potential of the signal or the electrostatic charges is greater than a critical value, a larger current generated is discharged to the ground Vss via the MOS transistor 10 by the hot electron effect and cannot flow into the internal circuit 10. Thus, the internal circuit 10 can be protected from damage.
However, the electric connection between the gate and source (or drain) of the MOS transistor 10 in the prior electrostatic discharge protective circuit is performed by using interconnections. Therefore, its layout takes a relatively larger space, resulting in a lower integration. To resolve this problem, a method of manufacturing an electrostatic discharge protective circuit, which takes a less space, shown in FIGS. 2A-2D is introduced. FIGS. 2A-2D are schematic cross-sectional views showing a method of manufacturing an electrostatic discharge protective circuit and a capacitor for DRAM.
Referring to FIG. 2A, a P-type semiconductor substrate 30 is provided. Device isolation regions 40, such as shallow trench isolation regions or field oxide regions, are formed on the substrate 30. An oxide layer and a polysilicon layer (not shown) are formed in order over the substrate 30, and then patterned to form a gate 70a consisting of a gate oxide layer 50a and a poly gate 60a. Next, using the gate 70a as a mask, N.sup.+ -type source/drain regions 80b and 80c are formed in the substrate on both sides of the gate 70a by, for example, ion implanting.
Referring to FIG. 2B, a silicon oxide layer (not shown) is formed over the substrate 30, and then anisotropically etched thereby to form spacers 90 on the vertical sides of the gate 70a.
Referring to FIG. 2C, at least one dielectric layer 100, such as a silicon oxide layer or BPSG, is formed over the substrate 30. The dielectric layer 100 is then patterned by photolithography and etching, thereby forming two contact windows 110 that expose the source/drain regions 80b and 80c and a contact window 105. Contact window 105 divides the gate 70a into two gates 70b and 70c consisting of gate oxide layers 50b and 50c and polysilicon layers 60b and 60c. Subsequently, parts of the substrate 30 exposed through the contact window 105 are ion implanted thereby to form a common N.sup.+ -type source/drain region 85 between the gates 70b and 70c.
However, in this step, there may be a deviation of alignment accuracy (AA) during photolithography and etching. For example, the common source/drain region 85 deviates slightly towards the gate 70c, resulting in a short channel between the common source/drain region 85 and the drain region 80c. Thus, the safe voltage that can be inputted to an internal circuit for a signal is lowered, causing a current leakage. If the safe voltage is greatly reduced, an operational error can occur. As to the lengthened channel between the common source/drain region 85 and the source region 80b making the safe voltage increase, it is undesirable for original circuit designs.
Referring to FIG. 2D, a conductive layer (not shown), such as a tungsten layer, is formed over the substrate 30 by, for example, chemical vapor deposition. Then, the conductive layer is patterned thereby to form two first conductive lines 120 and a second conductive line 121 in the contact windows 110 and 105, respectively, to electrically connect the source/drain 80b and 80c and the common source/drain region 85, respectively. Thus, the electrostatic discharge protective circuit for DRAM is completely manufactured.
As can be seen from the above, in the prior method of manufacturing an electrostatic discharge protective circuit for DRAM, the two gates and the common source/drain region are electrically connected to each other at one time by using the contact window between two gates. However, a deviation of alignment accuracy is inevitable and can shorten the channel between the common source/drain region and the source region or the drain region, causing a current leakage and even an operational error.